I see a variety of similarities between Tin whiskers… and my own: Elusive, thin, short, and never helpful.  And there is always the random single hair that frustrates you to no end.

Unfortunately, the costs associated with tin whiskers in the electronics, defense, health, and aerospace industries are astronomical compared to my need to shave once every two weeks.  Failure of products due to tin whisker growth can undermine an entire mission, scrap a program, or take a life.  I think about electronic pacemakers, our men and women traveling to space, or our servicemen and women flying at Mach speeds thousands of feet above the ground.

There has yet to be a definitive ruling made concerning the cause/prevention of whiskers, although pure tin components and plating seem to exhibit the highest likelihood of developing them.  Best practices at this time are to use a tin/lead mix with no greater than 97% tin.  However, RoHS regulations are throwing a wrench into this with its demands for lead-free products.  Some RoHS frequently asked questions are answered here.

This issue received significant attention at the IPC Technology Interchange this last December.  Also, the Center for Advanced Life Cycle Engineering at the University of Maryland (CALCE) and The Institute of Scientific and Industrial Research at Osaka University (ISIR) are putting on another International Symposium on Tin Whiskers this June.  The call for papers is still out.  Read more about this at PCB007. Proceedings from past Symposiums can be found here.

For a great overview of tin whiskers, be sure to check out the resources provided by NASA.  The pictures in this article have all been sourced from NASA.

Have you dealt with tin whiskers in your products/designs? What types of damage have they caused?  What are some of the things you have done to diminish the likelihood of them?

Homepage Image Original found here

A little over a  month ago I applied for membership with IEEE and joined a variety of societies pertaining to my line of business.  However, I have yet to really feel the benefit of membership aside from the barrage of emails asking me to sign up for conferences.  In an effort to effectively use my membership, I open the floor to you – my reader and potential IEEE confederate.  How have you taken advantage of the various services IEEE offers?  Has it been an effective networking/educational tool for you?  Share your story of how it has been a blessing – or a bust.

All the best,

Liam

click the picture to read more about the contact lenses

Below is a short description of what Flex Circuits are, pulled from Cirexx International’s Corporate website.

Flex Circuits are thin, lightweight, flexible, and durable. They can be designed to meet a wide range of temperature and environmental extremes. Flex Circuits are excellent for designs with fine line traces and high-density circuitry, and are more suited for dynamic applications and vibration conditions than are conventional printed wiring boards.

Flexible Circuits are built to bend, fold, twist, and wrap in extremely tight areas. Flex Circuits benefit designers faced with space restrictions. Cirexx has designed and fabricated Flex Circuits and Flex Cables with high density, lightweight, redundant circuitry for satellites and avionic instruments, advanced scientific sensors, flexible heating elements, devices and sensors, medical equipment and robotics, security devices and controls.

PCB East Website

LinkedIn Group

Do you, or any of your co-workers, plan on attending the PCB East 2009 Conference in Waltham-Boston, MA? If you do, you should join the LinkedIn group “PCB East Pre-Event Networking”. There you can begin to network with potential suppliers, customers, and colleagues. Why wait until that week to begin your research and to develop your relationships? Start now and ensure that your time there is spent efficiently. Feel free to discuss dinner options, happy hours, local events, and any other networking opportunities you might like to see occur that week.

Microflex circuitry can drive development programs for medical implants.

Technological advances in the medical field often hinge on the ability to create viable components and devices that are chemically compatible to human tissue and small enough to suit the internal workings of the human body. The medical device industry is at the forefront of the increasing trend of miniaturization, and manufacturers are faced with the challenge of effectively reducing the size of medical device elements.

Flexible circuits, key components in many medical devices, are subject to increasingly minute dimensions. Although many advances have been made in some aspects of flex circuit technology, until recently, there has been little progress in reducing the minimum conductive trace width and pitch dimensions. Extreme-resolution microflex (ERMF) circuitry is a manufacturing technology that may help reduce the minimum conductive trace and pitch dimensions that can be formed in a multilevel flex circuit. The process enables manufacturers to create devices that are small enough to fit the conditions of the human body. This technology has been used in blood glucose monitoring, angioplasty, and sight-restoration devices. The technology could lead to further innovations.

Developing Technology

As is the case with most technological advances, progress in medical device manufacturing is rarely linear. Rather, the advance of any particular science or technology often remains stagnant or shows only slight positive change for long periods, punctuated by incremental improvements.

Such is the case in the flexible circuit industry. For more than two decades before ERMF, the generally accepted minimum conductive trace was 0.075 mm, and acceptable pitch was 0.150 mm. As a result, progress in several critical application areas has been slow. For example, many development programs for applications in fields such as medical implants, drugs, and wearable military electronics have been at a standstill. The cause is a lack of flexible electronic circuitry small enough to suit the minute scale essential to such projects.

ERMF is based on semiconductor-level photolithography, thin-film processing (sputter deposition and ion milling), and electrochemical metal deposition. The process not only reduces the minimum conductive trace and pitch dimensions that can be formed in a multilevel flex circuit, but it also enables overall circuit areas to be reduced by a 200:1 factor. ERMF can produce six conductive-level flex circuits with minimum conductive trace and pitch dimensions of 0.005 mm and 0.010 mm, respectively, with overall circuit dimensions of 4.5 × 2.5 mm. Larger circuits with overall dimensions of 100 × 50 mm with 0.003-mm trace and 0.006-mm pitch have also been produced.

Traditional Microflex Circuit Manufacturing

Figure 1. (click to enlarge) The process for creating traditional flex circuitry is based on removal of layers to achieve a final component.

It may be helpful to review the traditional flex circuit manufacturing process compared with ERMF circuit process. Normal flex circuit manufacturing technology is based on
copper-clad polyimide sheet stock that is selectively wet-chemical etched to delineate and isolate the conductive traces. Because the wet-etch process removes the copper between the traces, the process is referred to as subtractive. A typical subtractive process uses the following four steps:

1. The precopper-clad polyimide is coated with dry-film photoresist.

2. The circuit pattern is exposed into the photoresist and developed such that the remaining photoresist pattern is protecting the copper areas that will ultimately become the conductive traces (see Figure 1a).

3. The resist-patterned copper-clad polyimide is then immersed in a chemical etch solution and the unprotected copper areas are etched away (see Figure 1b).

4. The photoresist is then removed, leaving the completed copper trace layer. Figure 1c describes the typical profile of a standard wet-etched subtractive process flex circuit.

Subtractive flex circuit manufacturing is a mature technology, and it has a 40-year history of improving and optimizing materials, manufacturing equipment, and processes. It performs extremely well for the many applications that require trace and space-width dimensions greater than 0.075 mm. It does not, however, address the needs of some medical device designers who are working on parts that require significantly smaller conductive traces and pitch dimensions. For example, circuits used for angioplasty procedures must be small enough and sufficiently flexible to be rolled into a cylinder for insertion into a blood vessel.

ERMF circuit process technology can address such needs. Traces may be sputter-deposited thin film (less than 0.001 mm thick). Or, traces can be electroformed (electrochemically deposited) up to 0.100 mm thick. ERMF traces can have thickness-to-width aspect ratios in excess of 3:1. This capability is critical for high-current density requirements such as radio-frequency induction systems. Because ERMF circuit traces are electroformed, the technology is sometimes referred to as an additive process.

Typical ERMF Process

ERMF circuits are based on a polyimide substrate. In most cases, the polyimide is cast. It is deposited onto a glass carrier plate in liquid form, spun to a specific uniform layer, and thermally cured. Possible single-layer thicknesses range from 0.007 to 0.025 mm. Multiple applications create thicker layers as needed. Trace metal may be pure gold, hard gold, copper, and gold-plated copper. In cases in which current-carrying capacity is not critical, sputtered thin-film traces of any metal are available. The following 11 steps outline a typical ERMF process:

1. Base (substrate) layer polyimide is cast onto a glass carrier plate. As stated above, the final cured cast thickness may vary from 0.007 to 0.025 mm, depending on the application and number of trace and dielectric layers required.

2. Once the base layer polyimide has been thermally cured, a blanket of adhesive and conductive seed metal is sputter deposited. Several metals are suited for this layer; however, the most common are titanium tungsten/gold and nickel chromium/gold (TiW/Au and NiCr/Au). The total thickness of this layer rarely exceeds 5000 å.

Figure 2. (click to enlarge) The ERMF process is an additive process rather than subtractive, enabling incremental buildup to desired thicknesses.

3. The next step is the depositing, imaging, and developing of the photoresist layer, which forms the reverse image of the trace pattern. The type and thickness of this photoresist layer depends on the application and minimum trace width. Circuits that require high-current-carrying capacity need photoresists that can form high-aspect-ratio features. For example, microinduction coils that require very small trace and pitch dimensions still require large cross-section areas. This is accomplished by maximizing the trace thickness-to-width aspect ratio. Figure 2a represents a cross section of a high-aspect-ratio imaged photoresist layer prior to electrochemical deposition of the trace material.

4. Once the resist pattern has been formed, the panel (carrier plate, deposited polyimide, seed metal, and imaged photoresist) is prepared for electrochemical metal deposition by attaching electrical contacts and chemically activating the exposed seed metal.

5. Using electroplating technology (anode, cathode, and electrolyte), the desired metal is deposited into the void areas formed by the imaged photoresist.

6. The photoresist is then stripped, leaving the completely formed traces still electrically connected by the seed metal (see Figure 2b).

7. The exposed seed metal is then removed by ion milling, leaving completely delineated and electrically isolated microtraces (see Figure 2c).

8. If the device being built is a single-conductive-layer ERMF circuit, the last step in the process is to deposit (cast) and image the polyimide coverlay.

9. If the device is a multiconductive-layer ERMF circuit, then a dielectric polyimide interlayer is deposited and cured as mentioned in step 2.

10. Via holes are formed, either by laser drilling or photoimaging the polyimide interlayer.

11. Steps 2 through 7 are repeated for each additional layer.

Process Limitations

To date, the ERMF manufacturing process is based on 150-mm2 panels. The technology is optimized for addressing circuits that have small overall dimensions. A general rule is that the smaller the overall area, the more efficient the processing and the higher the processing yield. The opposite is also true. The larger the overall size of the circuit, the less efficient the processing and the lower the process yield.

The maximum practical overall area is approximately 50.8 mm2. For example, the process can create a 100 × 12.7-mm or 35 × 35-mm circuit, but a 100 × 100-mm circuit might not be practical.

A second limiting factor is the number of conductive metal layers. Currently, circuits with six conductive layers have been successfully produced.

A third design restraint is the total area covered by the minimum feature size. For example, a 50 × 12.7-mm circuit with 25 0.005-mm traces and space running the 2-in. length is certainly practical. The same overall size circuit with 1000 0.005-mm traces would not be practical.

In the final analysis, it is the combination of these three factors of minimum feature size, overall area, and number of conductive layers that dictates the limits of the current ERMF process. As the technology matures, these limits will likely be relaxed.

Comparing Traditional and ERMF Processes

ERMF technology is not an extension or enhancement of the subtractive process, nor is ERMF in any way intended to replace traditional methods. It is a method used to form very complex circuitry in a small flexible format. ERMF addresses a critical need for flex circuitry with micron-scale features and overall circuit dimensions consistent with implant requirements.

When comparing ERMF with traditional methods, it is important to understand that each technology addresses a different area of the dimensional spectrum.

For this discussion, consider typical time-frequency code trace widths that are limited to 0.075 mm and larger. For ERMF, typical trace widths are 0.075 mm and smaller. Key parameters that affect cost and reliability are the overall area of the circuit, the number of conductive layers, and the minimum trace width and thickness (aspect ratio).

Overall reliability has two inter-related components: electrical reliability and mechanical reliability. Electrical reliability is a function of conductive trace current load capacity, dielectric strength of the polyimide interlayers, and breakdown voltage. Also, trace integrity (absence of electrical shorts and opens) is a critical component of circuit reliability.

In most cases, it is the circuit designer who defines the trace material, the design values of trace cross sections, and the polyimide’s thickness. These decisions are usually based on the bulk conductivity of the trace conductive material and dielectric strength of the polyimide interlayers. It is the manufacturer’s responsibility to form the traces within the specified design tolerance.

The ERMF additive process relies on high-resolution liquid photoresist and precise electroforming technology. Therefore, it is suited for producing accurately formed conductive cross sections that have reliable conductance and no electrical shorts open traces. Trace width and thickness dimensional tolerances of ±0.002 mm are the standard, although ±0.001-mm tolerances are possible when required. These values are easily confirmed by conventional measuring techniques.

It is the built-in process control of conductive trace dimensions and interlayer thicknesses that makes the ERMF circuits’ electrical characteristics consistently reliable.

The dimensional consistency of trace cross sections is more difficult to control using etching processes. The isotropic nature of the chemical etch (subtractive) process is inherently difficult to control. This inconsistency usually limits the technology to trace and space dimensions of 0.075 mm or greater. That said, however, the etch industry has decades of experience and has made significant process improvements to optimize process technology and controls. Such manufacturers can produce flex circuits with consistently reliable electrical characteristics within the 0.075-mm and larger dimensional spectrum.

Mechanical reliability of all types of flex circuits is a function of trace width, overall size, the number of conductive vias, and layers. During the manufacturing process, after the traces have been formed and before the subsequent dielectric interlayer or coverlay has been deposited, the tiny conductive traces are susceptible to physical damage. However, after the deposition of the cast polyimide coverlay, the embedded circuitry is remarkably robust and capable of sustained continuity after being flexed over a 0.125-mm radius. A second factor is that because the ERMF circuits are seldom larger than 2.5 mm², it is possible to encapsulate the entire circuit after integrated circuit chips have been attached and I/O connections have been made.

Similarly, etched flex-circuit devices are highly reliable once the protective cover layer has been deposited. The large physical size of these devices precludes total encapsulation. Acceptable bend radii are much larger.

Traditional flex circuits are produced with more than six layers. However, the density of traces is far less. More-densely packed six-layer ERMF circuits could contain as much information as traditional circuits, which usually require several more layers. ERMF circuits address a manufacturing need that cannot be accomplished with other processes. It is possible that as ERMF technology matures, circuits with many more layers may be possible. However, the two technologies do not compete with each other. The advantage of ERMF is that it enables design engineers to do things that have not previously been possible.

ERMF Costs

The final cost of any flexible circuit is a function of size, trace density, the number of layers, and the number of conductive via holes. Yet, pricing for ERMF does not fit nicely into the cost-per-square-centimeter model in the same way that the etching process does. Because subtractive methods cannot create parts of the size and dimension of ERMF, it would be unfair to compare the two. ERMF providers work with designers to establish design-to-cost objectives and assist them in modifying the circuit to take advantage of ERMF processes while keeping the cost within targets.

At this point, ERMF is considered more like a custom project, and designers should take that into consideration when planning to use microflex circuits created with the additive process.

Conclusion

ERMF is still a relatively new process that holds far more potential than is currently being tapped. The nature of the process enables part consistency and reliability. And the minute dimensions of the resulting microcircuits are very exciting because they will enable manufacturers to create even smaller and more-effective medical devices. As device designers become aware
of the technology, they should consider using it for miniature circuits for implants.

Luke Volpe is director of engineering at Dynamics Research Corp.’s Metrigraphics division (Wilmington, MA). He can be reached at lvolpe@drc.com.